1. Mixed signal integrated circuits
2. Wireless/Wireline communication ICs
A 2.4 GHz Reference-less Wireless Receiver for 1Mbps QPSK Demodulation (ISCAS’10 & TCAS-I’12)
A 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 mm x 1.55 mm.
A 10-Gbps CMOS Single Chip Optical Receiver with 2-D Meshed Spatially-Modulated Light Detector (CICC’09 & JSSC’11)
This paper describes the design of a 10-Gb/s fully integrated CMOS optical receiver, which consists of a novel spatially-modulated photo detector (SMPD), a low-noise trans-impedance amplifier (TIA), and a post limiting amplifier on a single chip. The bandwidth of proposed meshed SMPD can be boosted up to 6.9 GHz under a reverse-biased voltage of 14.2 V. The operating speed of optical receiver is improved by 3 X compared to the prior art. To compensate the responsivity of on-chip CMOS PD, a high-gain TIA with nested feedback and shunt-peaking is proposed to achieve low-noise operation. The optical receiver is capable of delivering 25 kΩ conversion gain when driving 50 Ω output loads. Implemented in a generic 0.18-μm CMOS technology, the chip area is 0.95 mm by 0.8 mm. The input sensitivity of the optical receiver is about 18 App, and the measured responsivity of the photo detector is about 29 mA/W. Incorporating external PD with responsivity of 0.65 A/W, the input sensitivity of the optical receiver is -19 dBm for BER less than 1E-10 under 127 PRBS test pattern. The receiver core and output buffer respectively drain 118 mW and 27 mW from a single 1.8 V supply.
A 7.1 mW, 10-GHz All Digital Frequency Synthesizer with Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology (ISSCC’09 & JSSC’10)
A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 μs locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm x mm.
A 3-10 GHz, 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System (ISSCC’07 & TVLSI’12)
A 3-10 GHz, 14 Band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system is presented. Based on a single PLL and two-stage frequency mixing architecture, the image spurs are suppressed below -45dBc and improved by more than 22 dB incorporating with I/Q calibration for the single side band mixers. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply.
A Wide-Range Burst Mode Clock and Data Recovery Circuit (A-SSCC’06)
This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18-μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 1E-10.
A Single Chip 2.5 Gbps CMOS Burst Mode Optical Receiver (VLSI’06 & TCAS-I’09)
This paper describes the design of a 2.5-Gb/s burst-mode optical receiver in a 0.18-μm CMOS process. A dual-gain-mode transimpedance amplifier (TIA) with constant damping factor control is proposed to tolerate a wide dynamic range input signal. By incorporating an automatic threshold tracking circuit (ATC), the TIA and limiting amplifier (LA) are dc coupled with feedforward offset cancellation. Dual-band filters are adopted in the ATC for a rapid response time while keeping the tracking error small. By integrating both a TIA and a post-LA in a single chip, the burst-mode receiver provides a conversion gain of 106 dBΩ in the high gain mode, 97 dBΩ in the low gain mode, and a 3-dB bandwidth of 1.85 GHz. The measured input sensitivity, overload level, and dynamic range of the optical receiver are -19 dBm, -2 dBm, and 17 dB, respectively. The response time is less than 50 ns. Operating under a single 1.8-V supply, this chip dissipates only 122 mW.
A Dual-Band Quad-Mode Δ-Σ Frequency Synthesizer (RFIC’07)
This paper describes the design of a dual-band, four-mode Delta-Sigma frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a third order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 musec. A charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-μm CMOS process, the chip size is 1.95 mm x mm. The total power consumption is 19.54 mW from a 1.8 V power supply.
A Low Power Programmable PRBS Generator and A Clock Multiplier Unit for 10 Gbps Serdes Applications (TCAS-I’08)
This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. PRBS generator is capable of producing 2^7-1, 2^1o-1, 2^15-1, 2^23-1, and 2^31-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps (rms), and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18-μm CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87 mW.
Miniaturized 3-Dimensional Transformer Design (TCAS-I’07)
This paper presents novel three-dimensional (3-D) symmetric passive components, including inductors, transformers, and balun. Layout areas of these components are drastically reduced by 32% to 70%, while the symmetry of the input and the output ports is still maintained. The inductance mismatch in the 3-D transformer is less than 0.1%, and the coupling coefficient can be up to 0.77. The 3-D balun manifests less than 0.6-dB gain mismatch for 10-GHz range, and the phase error is less than 7 degree from 1- to 10-GHz frequency range according to measurement results. Furthermore, the self-resonant frequency of the proposed architecture is improved by 32% to 61% in contrast to their planar counterparts. On the other hand, the quality factor is degraded by less than 2 for the sake of using lower metal layers. The distributed capacitance model is utilized to validate their superiorities in self-resonant frequency . All the devices are fabricated in a generic 0.18-μm CMOS process.
A 1.8V, 10Gbps Fully Integrated CMOS Optical Receiver Analog Front End (JSSC’05)
A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-μm CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV(pp). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB and 3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12 dBm at a bit-error rate of 1E-12 with a 2^31 – 1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 μm x 1796 μm.