【演講訊息】Design of High-Speed Equalizers in Modern Data Link Systems

時間地點:101年9月25日(二)下午2:30-4:10 交大工程四館202教室
This talk presents the general design theory and methodology of modern equalizers for high-speed wireline applications. Three major topologies, FFE, analog, and DFE are introduced with detailed design skills. A few silicon proven design examples are included as case study.
Jri Lee is Professor of Electrical Engineering at National Taiwan University. His research includes wireless and wireline transceivers, high-speed communication systems, and mmwave techniques. He is serving or has served as SSCS Distinguished Lecturer, TPC members of ISSCC, VLSI Symposium, and A-SSCC. He received the Beatrice Winner Award at ISSCC2007 and Takuo Sugano at ISSCC2008.
交大電子 廖小姐
TEL: 03-5712121*54189
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【演講訊息】RF Receivers, CDR, and Deserializer

國際知名學者 Prof. Behzad Razavi (UCLA)蒞臨台灣演講,以下分別為新竹、台北場次。
歡迎 有興趣的師生及同仁到場聆聽,詳細內容請參閱附檔活動海報。

講題:A Harmonic-Rejecting LNA for Broadband RF Receivers
時間:101年9月19日(三) 15:50-17:00
地點: 交大工程四館國際會議廳

講題:A 25-Gb/s 5-mW CMOS CDR/Deserializer
時間:101年9月20日(四) 17:00-18:00
地點: 台大博理館101國際演講廳

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【演講訊息】Design Consideration for ESD and Latch-up (Aug/27, 2012)

講員:Dr. Tzung-Yin Lee (Skyworks)
時間:2012年8月27日(一) 下午 2:00 ~ 3:00
大綱:Design Consideration for ESD and Latch-up ESD and latch-up are two of the most frequent reliability issues for commercial IC’s. They contribute more than 25% of total IC failure during manufacturing and in the field. While often overlooked in the design process, as other factors such as performance and cost always attract most of the attention, design for reliability eliminates major hurdle in product introduction. The presentation describes typical reliability requirement, testing, and qualification for commercial IC’s and the ever-increasing challenge posed by advanced CMOS technology. Various approaches that are commonly adopted by industry to ensure ESD robustness and latch-up immunity will be discussed. The emphasis will be mainly for custom analog and RF IC application.

主講人簡介:Tzung-Yin Lee joined Skyworks in March 2003, where he is presently the senior manager in charge of Foundry Technology Modeling, ESD, and Device Characterization group. From 2001 to 2003 he was with Maxim Integrated Products working on WLAN product development. From 1997 to 2001, he was with Conexant Systems, formerly Rockwell Semiconductor Systems, working on the development of the RF front-end device for Bluetooth and coreless application.?He received the B.S. degree from National Chiao Tung University, Hsin-Chu, Taiwan, in 1991, and the M.E. and Ph.D degrees from University of Florida, Gainesville, Florida, in 1992 and 1997, respectively. He has authored and coauthored more than two dozens of research papers in high-speed and high-frequency device modeling for RFIC design application.

IEEE SSCS Taipei Chapter
國立台灣大學電機工程學系 / 國立台灣大學電子工程學研究所
聯絡人:王邦全  (02) 3366-3700 ext 6430

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【演講訊息】Sub-millimeter Wave CMOS Integrated Circuits and Systems


第一場:101年8月6日(一)上午10:00-11:30 台大電機二館 124 會議室
第二場:101年8月6日(一)下午15:30-17:00 交通大學工程四館528會議室


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【演講訊息】Sub-millimeter Wave CMOS Integrated Circuits and Systems (Aug/02, 2012)

講員:Prof. Kenneth K. O (UT Dallas)
時間:101年08月02日(四) 15:20~17:00
地點:國立交通大學工程四館 424 會議室
大綱:CMOS (Complementary Metal Oxide Silicon) integrated circuits (IC’s) technology is emerging as a means for realization of capable and affordable systems that operate at 200 GHz and higher. The potential applications include spectroscopy for detection of harmful and dangerous chemicals, active and passive imaging for detection of concealed weapons and materials, short range radars, and high data rate wireless and wireline communication. The performance of devices as well as signal sources and detectors operating between ~400 and 900 GHz fabricated in silicon CMOS technologies will be discussed. Based on these, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The potential applications and challenges make the sub-millimeter wave CMOS an exciting area of research for the silicon integrated circuits community.

主講人簡介:Kenneth O received his S.B, S.M, and Ph.D degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, Cambridge, MA in 1984, 1984, and 1989, respectively. From 1989 to 1994, Dr. O worked at Analog Devices Inc. developing sub-micron CMOS processes for mixed signal applications, and high speed bipolar and BiCMOS processes. He has been a professor  at the University of Florida, Gainesville from 1994 to 2009.  He is currently the director of Texas Analog Center of Excellence and TI Distinguished Chair Professor of Analog Circuits and Systems at University of Texas at Dallas. His research group is developing circuits and components required to implement analog and digital systems operating between 1 and  THz using silicon IC technologies. He was the general chair of the 2001 IEEE Bipolar/BiCMOS Circuits and Technology Meeting . Dr. O has also served as an associate editor for IEEE Transaction on Electron Devices from 1999 to 2001. Dr. O was a  member of ADCOM of IEEE Solid-State Circuits Society between 2009-2011. He chairs the Meetings Committee of IEEE Solid-State Circuits Society. He has authored and co-authored ~200 journal and conference publications, as well as holding nine patents. Dr. O has received 1996 NSF Early Career Development Award. Prof. O is also an IEEE Fellow.

IEEE Solid-State Circuits Society Taipei Chapter
國立交通大學前瞻奈米電子與系統研究中心 頂尖計畫
聯絡人:廖小姐 (03) 5712121 ext. 54189

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Advanced Short Course on “Digital RF and Digitally-Assisted RF” (Apr / 10, 2012)

時間: 101/4/10(二) 9:00-17:00
地點: International Convention Center, CPT Building, National Chiao Tung University (交通大學 交映樓 1F 國際會議廳)
講者: Robert Bogdan Staszewski, Associate Professor, Delft University of Technology, Department of Microelectronics, Delft, Netherlands, IEEE Fellow, Formerly CTO of the Wireless Digital RF Processor (DRPTM) group of Texas Instruments in Dallas, Texas, USA

講者簡歷: R. Bogdan Staszewski received BSEE (summa cum laude), MSEE and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRPTM) group with a mission to invent new digitally-intensive approaches to traditional RF functions. Dr. Staszewski has served as a CTO of the DRP group between 2007 and 2009. Since July 2009 he is Associate Professor at Delft University of Technology in the Netherlands. He has co-authored one book, four book chapters, 135 journal and conference publications, and holds 100 issued and 50 pending US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He is an IEEE Fellow.

課程內容: The past several years have successfully brought all-digital techniques to commercial wireless radio frequency (RF) synthesizers and transmitters, as well as digitally-intensive techniques to receivers. In addition, digital assistance is applied to RF circuits to improve performance and power consumption. This new paradigm revolves around a bold premise of “the superiority of a time-domain operation over the traditional voltage-domain operation” in which the time-stamps, rather than the voltage or current levels, are the information carrier. This approach works surprisingly well in nanoscale CMOS processes, being nowadays the mainstream process technology for consumer electronics, with their rising and falling transition times on the order of 10 picoseconds as well as extremely low energy consumption due to the fact that only 100 or so electrons are involved in each transition. This new paradigm has been successfully exploited by this instructor while at Texas Instruments in Dallas, Texas, USA to gain significant improvements in cost, area/volume, energy consumption and integration level of wireless electronics. Consequently, the majority of the 1.6 billion cell phones produced annually are now based on this approach.
This short course will introduce basic concepts of the digital RF approach and walk through the major building blocks that comprise the new RF transceiver architecture: 1. All-digital phase-locked loop (ADPLL) comprising: digitally-controlled oscillator (DCO), time-to-digital converter (TDC), and digital loop filter; 2. All-digital transmitter featuring ADPLL with wideband modulation capability, and comprising digitally-controlled power amplifier (DPA) that acts as an RF digital-to-analog converter (RF-DAC); 3. Direct-sampling discrete-time receiver comprising switched-cap circuits that perform various FIR and IIR filter operations. Case studies of successful commercial realizations will be given.

輔助教材:Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.

課程大綱:The total of six lecture hours will give the following exposure to the three main topics: (1) ADPLL: 3 hours; (2) DPA: 1 hour; (3) discrete-time RX: 1 hour; in addition to 1 hour introduction.
1) Introduction (1hrs)
a. New paradigm of RF circuit design in a nanometer-scale CMOS
b. Digital RF and digital assistance of RF
c. Examples of on-chip calibration and self-healing techniques d. Survey of RF-SoC’s
2) Digitally-controlled oscillator (DCO)
a. Phase noise modeling and simulation
b. DCO interface: sigma-delta modulation, dynamic element matching, DCO gain normalization
3) Phase-domain frequency synthesis: all-digital PLL (ADPLL)
a. Principles of phase-domain frequency synthesis
b. ADPLL closed-loop behavior
c. Direct frequency modulation of ADPLL
d. Alternative TX architectures using ADPLL and PA regulator
e. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design
4) Time-to-digital converter (TDC)
a. Circuit design
b. Metastability
5) Digitally-controlled power amplifier (DPA)
a. Principles of DPA
b. DPA modeling and non-linearities; predistortion
c. Case study of digital RF amplification
6) Discrete-time (DT) receiver
a. Signal processing of a DT mixer: IIR, FIR and decimation
b. Front-end to ADC path circuit design
c. DT receiver simulation

報名資訊: 參加對象:學術界與業界相關研究人員、師生、工程師。 報名日期:即日起至101年4月8日止。

1) 一律線上報名,報名網址:http://tinyurl.com/7muf4p3
2) 報名費:非IEEE會員NT$1500;IEEE會員/學生:NT$800 ※恕不退費(請於報到當天領取收據)※含〔講義〕及〔午餐〕
3) 繳費方式:
i. 支票或匯票:請於4月8日前將支票或匯票寄至『30010新竹市大學路1001號 國立交通大學電子系 廖文瑜小姐收』 支票或匯票抬頭:『廖文瑜』,請在支票或匯票背面用鉛筆註明〔單位〕〔姓名〕。
ii. 郵局ATM轉帳:立帳郵局:700,郵局帳號:0061109 0356621,戶名:廖文瑜。
4) 洽詢 E-mail: sscstpe@gmail.com

主辦單位:IEEE SSCS Taipei Chapter

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Seminar: Imaging neural plasticity and drug effects in the brain (27/Dec/2011)

Title: Imaging neural plasticity and drug effects in the brain
Speaker: Kai-Hsiang Chuang, PhD
When: 27/Dec/2011 (Tue.) 10:00 – 11:00
Where: Rm#528, Engineering Building 4th, NCTU


Recent advances in magnetic resonance imaging (MRI) have opened up new perspectives for understanding brain function and its plasticity after nerve damage, degeneration or even in the process of learning and memory. Using functional MRI (fMRI), reorganization of the cortical representation can be detected after the peripheral nerves deafferentation or digit amputation. To detect the more trivial changes during learning and memory, we established functional connectivity MRI that identifies neural areas that form a synchronous network. We demonstrated that memory network can be visualized after maze training. Furthermore, we showed that synchrony rather than activity in the brain can be modulated by receptor targeted pharmaceuticals, which indicate a different drug mechanism. The translation of these methods will facilitate our understanding of brain plasticity, early diagnosis of dementia, and evaluation of drug efficacy.


Speaker Biography

Kai-Hsiang Chuang received the B.S., M.S, and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan in 1995, 1997, and 2001, respectively. In the graduate school, he studied image processing and analysis methods for improving the detectability and reliability of functional MRI to study the human brain function. During 2001-2003, he was an associated MRI scientist in the Department of Radiology, Kaohsiung Veterans General Hospital, Taiwan, where his researches include acupuncture fMRI, automatic pattern analysis of lung perfusion, and voxel based morphometry analysis in patients. From 2003 to 2007, he was a post-doctoral research fellow with Dr. Alan P. Koretsky in the Laboratory of Functional and Molecular Imaging, National Institute of Neurological Disorders and Stroke, National Institutes of Health, Bethesda, Maryland, USA. In this period, he changed his focus to develop molecular imaging methods that allow imaging functional and metabolic activity of cells in small animals. He joined the Singapore Bioimaging Consortium, A*STAR, Singapore in 2008. He is currently the leader of the MRI group and a joint scientist at the Clinical Imaging Research Centre, National University of Singapore. His current research focuses are on the development translational methods to image neural activity, metabolism, and connectivity for understanding neural plasticity and for early detection of neurodegenerative diseases.


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Self-Healing CMOS Transmitter for Millimeter-Wave Broadband Digital Communications

Title:Self-Healing CMOS Transmitter for Millimeter-Wave Broadband Digital Communications
Presenter:Jenny Yi-Chun Liu
Time:2011/10/19 (Wed.) 13:30-14:30
Place: ED 102, National Chiao Tung University
Maphttp://guidetour.nctu.edu.tw/ch/ind_01.html       (校園導覽-學術單位->電機學院->電子工程系所->工程四館 102 室)
Registration Fee: For free


The explosive growth of portable wireless communications has spurred the need for technologies that enable high data rate (>4 Gbps) within short distance (~10 m) with low power consumption, low cost, and small form factor for portable links/systems. The 57-65 GHz band is ideal for such operation at short distance due to its broad bandwidth (1.2 GHz/channel and total 4 channels) and high channel reusability, due to high attenuation rate over the air. With increasing device cut-off frequencies due to aggressive device scaling, the super-scaled CMOS technology (ft and fmax >150 GHz in N65 GP process) is promising for designing highly integrated circuits operating at millimeter-wave frequencies. Nevertheless, CMOS technology also poses its own deficiencies in high frequency front-end circuit implementation. The design challenges come from issues such as the low breakdown voltage of the transistor, the conductive substrate, the lossy metal layers, and the lack of accurate device models at high frequencies (>25 GHz). These drawbacks translate to constrained transmitted output power, low efficiency, and poor linearity. Additionally, the process variation is increased with decreased device feature sizes that render circuit performance yield low.

In this talk, I will present a new paradigm for millimeter-wave transmitter architecture design. This architecture facilitates two levels of control to ensure the circuit performance and yields. It contains a local-level AM-to-AM and AM-to-PM control and a global self-healing control by using on-chip temperature/power/envelope sensors and current control knobs/actuators to monitor and correct transmitter performance according to pre-specified performance metrics (up to 16-QAM modulation) and performance-yield requirement. The transmitter, being part of a fully integrated radio-on-a-chip for multi-gigabit digital communications, can therefore self-diagnose and heal its own performances against harsh environmental stresses under deep-scaled CMOS process variations and aging situations.


Jenny Yi-Chun Liu received the B.S. degree in Electronics Engineering from National Chiao Tung University, Taiwan, and the M.S. and Ph.D degrees in Electrical Engineering from University of California, Los Angeles, in 2005, 2008, and 2011, respectively. She is currently a postdoctoral scholar in High Speed Electronics Lab, UCLA. Her research interests include millimeter-wave/THz integrated circuits, transceiver linearization, and ultra low-power wireless circuits and systems.




廖文瑜 SSCS Taipei Chapter助理 E-mail:sscstpe@gmail.com

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Short Courses on Oscillator Phase Noise and CMOS Power Amplifier Design

Title:Short Courses on Oscillator Phase Noise (morning session) and CMOS Power Amplifier Design (afternoon session)
Presenter:Prof. Ali Hajimiri (California Institute of Technology)
Time:2011/08/01 (Mon.) 9:00~12:00 (AM), 2:00~5:00 (PM)
Place: National Chiao Tung University (新竹市大學路1001號 工程四館 國際會議廳)
Maphttp://guidetour.nctu.edu.tw/ch/ind_01.html (校園導覽-學術單位->電機學院->電子工程系所->工程四館B1國際會議廳)
Register: http://tinyurl.com/3u2dc67 (短期課程免費報名 請踴躍參加)


Oscillator Phase Noise: In this tutorial, we will review the fundamental noise processes in oscillators and see how the intrinsic noise is converted into phase noise. We will develop a time-varying model for oscillator noise and see its implications for free running oscillators and phase locked loops. CMOS Power Amplifier: In this tutorial, we will review the challenges of a CMOS power amplifier design and investigate innovative solutions to overcome the low breakdown voltage and high passive loss to fully integrate CMOS power amplifiers. We will also investigate power generation at mm-wave and THz frequencies in CMOS.


Ali Hajimiri received his Ph.D. degree in electrical engineering from the Stanford University. He was with Philips Semiconductors, Sun Microsystems, and Lucent Technologies (Bell Labs), Before joining the Faculty of the California Institute of Technology, Pasadena, in 1998, where he is Thomas G. Myers Professor of Electrical Engineering and the director of Microelectronics Laboratory. His research interests are high-speed and RF integrated circuits for applications in sensors, biomedical devices, and communication systems. Dr. Hajimiri was selected to the TR35 top innovator’s list (formerly TR100) in 2004. He is a Fellow of IEEE and has served as a Distinguished Lecturer of the IEEE Solid-State and Microwave Societies. He was a co-recipient of the IEEE Journal of Solid-State circuits Best Paper Award, the International Solid-State Circuits Conference (ISSCC) Jack Kilby Outstanding Paper Award, a two-time co-recipient of CICC best paper award. In 2002, he co-founded Axiom Microdevices Inc., whose fully-integrated CMOS PA has shipped more than one hundred and fifty million units, and was acquired by Skyworks Inc. in 2009.




廖文瑜 SSCS Taipei Chapter助理 E-mail:sscstpe@gmail.com

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2011 VLSI Design/CAD Symposium

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