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On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

2018/01/17 By ctsai37

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. In this work, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The proposed ESD device uses a P+ and N+ junction contact with silicide to shorten the path of SCR, which can reduce the trigger voltage and turn-on resistance to get higher ESD robustness. As compared to the prior ESD protection devices, the experimental results show that the proposed device has the better FOMs. The proposed device verified in this work will be a useful ESD protection solution for the high-speed I/O applications in the nanoscale CMOS technology.

 

Publication: JT Chen, CY Lin, MD Ker, “On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology,” IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 3979-3985, Oct. 2017.

Filed Under: 研究成果

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