A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through … [Read more...] about Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
研究成果
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
A novel horizontal n-channel junction field effect transistor (n-JFET) device is proposed and verified in a 0.25-µm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to … [Read more...] about A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology
The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this work. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon … [Read more...] about Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology
System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip
A co-packaged methodology using Transient Voltage Suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection is proposed in this work. The design methodology is verified in a high-voltage silicon-on-insulator (SOI) process for CAN transceiver chip and an 0.8-mm bipolar process for TVS chips. The I-V curves of … [Read more...] about System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip
On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly … [Read more...] about On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology