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交大 307 實驗室

Mixed-Signal, Radio-Frequency, and Beyond

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    • 天下雜誌報導
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    • Data Converter ICs
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    • 吳介琮
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    • 郭建男
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    • 王毓駒
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Main Content

研究成果

  • Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

    Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
  • A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

    A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
  • Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology

    Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology
  • System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip

    System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip
  • On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

    On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
  • A Digitally Dynamic Power Supply Technique for 16-Channel 12V-Tolerant Stimulator Realized in a 0.18-μm 1.8-V/3.3-V Low-Voltage CMOS Process

    A Digitally Dynamic Power Supply Technique for 16-Channel 12V-Tolerant Stimulator Realized in a 0.18-μm 1.8-V/3.3-V Low-Voltage CMOS Process
  • A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control

    A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control
  • A 81-dB Dynamic Range 16-MHz Bandwidth DS Modulator Using Background Calibration

    A 81-dB Dynamic Range 16-MHz Bandwidth DS Modulator Using Background Calibration
  • A 10-Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation

    A 10-Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation
  • Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology

    Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology
  • Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits

    Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits
  • Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

    Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
  • A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC

    A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
  • Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection

    Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection
  • ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process

    ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process
  • New design of 2 × VDD-tolerant power-rail ESD clamp circuit for mixed-voltage IO buffers in 65-nm CMOS technology

    New design of 2 × VDD-tolerant power-rail ESD clamp circuit for mixed-voltage IO buffers in 65-nm CMOS technology
  • New 4-bit transient-to-digital converter for system-level ESD protection in display panels

    New 4-bit transient-to-digital converter for system-level ESD protection in display panels
  • Stimulus driver for epilepsy seizure suppression with adaptive loading impedance

    Stimulus driver for epilepsy seizure suppression with adaptive loading impedance
  • A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband

    A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband
  • A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13-um CMOS

    A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13-um CMOS

佈告欄

Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple … [Read More...] about Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

A novel horizontal n-channel junction field effect transistor (n-JFET) device is proposed and verified in a 0.25-µm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions … [Read More...] about A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology

The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this work. Owing to … [Read More...] about Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology

System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip

A co-packaged methodology using Transient Voltage Suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection is proposed in this … [Read More...] about System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chip

新聞

恭賀 翟芸論文入選 ISSCC 2012

恭賀 翟芸同學投稿論文 “A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC” 入選 2012 IEEE International Solid-State Circuits Conference (ISSCC). … [Read More...] about 恭賀 翟芸論文入選 ISSCC 2012

恭賀 曾偉信、范啟威論文入選 ISSCC 2011

恭賀 曾偉信、范啟威同學投稿論文 “A 12-Bit 1.25-GS/s DAC in 90nm CMOS with > 70dB SFDR up to 500MHz” 入選 2011 IEEE International Solid-State Circuits Conference (ISSCC). … [Read More...] about 恭賀 曾偉信、范啟威論文入選 ISSCC 2011

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