A 2-1 MASH switched-capacitor delta-sigma modulator (DSM) was fabricated using a 65 nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter-based opamp and a source-coupled-pair-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5 MS/s sampling rate, this chip consumes 175 uW from a 1 V supply. For a 25 kHz signal bandwidth, it achieves a 96.1 dB SNR, a 94.6 dB SNDR and a 98.5 dB DR. Its active area is 1.13×0.34 mm^2.

Publication: (1) S-H Liao and J-T Wu, “A 1-V 175-uW 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques,” *IEEE Journal of Solid-State Circuits*, Vol. 54, No. 9, pp. 2523-2531, Sept. 2019. (2) S-H Liao and J-T Wu, “A 1 V 175 uW 94.6 dB SNDR 25 kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques,” *2018 IEEE Custom Integrated Circuits Conference,* April 2018.